GE VMIVME-7805 VMEBus SBC Motherboard

Introduction

The ACC-0603RC is a Rear Transition Module (RTM), designed to transition the

V7865 I/O signals from the VME P2 connector to standard I/O connectors.

The panel I/O access provides:

• One serial port connector (DB9), supporting both RS232 and RS422

• Two standard USB 2.0 connectors

• Digital Visual Interface-Digital (DVI-D) video support

• One Serial ATA (SATA) connector

The onboard I/O access provides:

• One PIM I/O interface

• One SATA connector

See Figure 1-1 on page 12 for an illustration of the board and connector layout.

The VME P2 connector carries all associated signals. All signals are routed from the

single board computer (SBC) (installed in the front of the chassis) through the

backplane to the ACC-0603RC P2 connector. Figure 1-2 on page 13 is an illustration of

the ACC-0603RC installed in the VME rear I/O.

Features

The following brief overview of principal features illustrates the flexibility and

performance that is available with the VMIVME-3113A Board:

• 64 differential or single-ended inputs

• Powers up in AUTOSCANNING MODE - no software initialization required

• Continually digitizes all input channels and stores the results in a dedicated

channel dual-port register (AUTOSCANNING MODE)

• Six operating modes

— AUTOSCANNING MODE *

— RANDOM POLL MODE

— RANDOM INTERRUPT MODE

— SCANNING POLL MODE

— SCANNING INTERRUPT MODE

— AUTOSCANNING MODE with BIT

* Only for gain = 1 and a minimum of 16 channels.

• VMEbus interrupts may be programmed to interrupt upon completion of a

single A/D conversion, or upon completion of a 16 through 64-channel scan

(see “Analog-to-Digital (ADC) Control and Timing” on page 26)

• User-programmable interval timer supports scanning of all channels at periodic intervals

• Jumper-programmable gains of 1, 10, 100, 200 and 500

• Selectable A/D ranges of 0 to +10V, ±5V and ±10V

• Low-level and high-level inputs: ±10mV to ±10V

• Optional low pass filter

• Overvoltage protected inputs

• 5 x 106

Ω input impedance differential and 2x106

Ω input impedance

single-ended

• 33 kHz conversion rate at GAIN<500 (23kHz for GAIN = 500)

• Selectable output code: binary, offset binary, two's complement with sign extension

• Front panel Fail LED is under program control and may be used for any purpose

• Board ID register

The VMIVME-5576 does not need to be initialized unless interrupts are used.

If interrupts are used, vectors and interrupt levels must be written to on-board registers and interrupts must be set.

Each node on the system has a unique identification number between 0 and 255.

The node number is determined by placing jumpers on the board during hardware system integration.

The node number can be read by software by accessing the on-board registers. 

In some applications, the node number helps determine the function of the node.

The IS200SAMBH1A is an acoustic monitoring terminal board that is part of the GE Speedtronic Mark VI gas turbine controller.

The dual terminal board adds 18 inputs to the acoustic monitoring system via 36 terminals on the terminal strip for two-wire input connections.

The board also has terminal blocks with 36 terminal connections for two-wire buffered outputs for a total of 18 outputs.

Typically, these outputs are used to monitor voltage signals.

To protect against high-frequency noise from external sources, the IS200SAMBH1A is equipped with a passive electromagnetic interference (EMI) filter.

Write data is stored in the local SRAM and broadcast to other Reflective Memory nodes via a high-speed fiber optic data path.

Data transfers between nodes are software transparent, so there is no I/O overhead.

Transmit and receive FIFOs buffer data during peak data rates to optimize CPU and bus performance and maintain high data throughput.

Reflective memory also allows interrupts to one or more nodes by writing to byte registers.

These interrupt (tertiary, user-definable) signals can be used to synchronize system processes or to follow any previous data.

Interrupts always follow the data to ensure that the data is received before the interrupt is acknowledged.