GE IS400TVBAH2B Vibration Terminal Board

Part Number IS400TVBAH2B Manufacturer General Electric Country of Manufacture

As Per GE Manufacturing Policy Series Mark VI Function Module Availability 

IS420UCSBH4A Module manufactured by General Electric as part of the Mark VI/VIe Series

used in gas turbine sppedtronic control systems View More IS220PSCAH1B

Module manufactured by General Electric as part of the Mark VI/VIe Series used

in gas turbine sppedtronic control systems View More IS220PDIAH1B Module manufactured

by General Electric as part of the Mark VI/VIe Series used in gas turbine sppedtronic

control systems View MoreModule manufactured by General Electric as part of the Mark VI/VIe

Series used in gas turbine sppedtronic control systems

The VMIVME-5576 does not need to be initialized unless interrupts are used.

If interrupts are used, vectors and interrupt levels must be written to on-board registers and interrupts must be set.

Each node on the system has a unique identification number between 0 and 255.

The node number is determined by placing jumpers on the board during hardware system integration.

The node number can be read by software by accessing the on-board registers. 

In some applications, the node number helps determine the function of the node.

The IS200SAMBH1A is an acoustic monitoring terminal board that is part of the GE Speedtronic Mark VI gas turbine controller.

The dual terminal board adds 18 inputs to the acoustic monitoring system via 36 terminals on the terminal strip for two-wire input connections.

The board also has terminal blocks with 36 terminal connections for two-wire buffered outputs for a total of 18 outputs.

Typically, these outputs are used to monitor voltage signals.

To protect against high-frequency noise from external sources, the IS200SAMBH1A is equipped with a passive electromagnetic interference (EMI) filter.

Write data is stored in the local SRAM and broadcast to other Reflective Memory nodes via a high-speed fiber optic data path.

Data transfers between nodes are software transparent, so there is no I/O overhead.

Transmit and receive FIFOs buffer data during peak data rates to optimize CPU and bus performance and maintain high data throughput.

Reflective memory also allows interrupts to one or more nodes by writing to byte registers.

These interrupt (tertiary, user-definable) signals can be used to synchronize system processes or to follow any previous data.

Interrupts always follow the data to ensure that the data is received before the interrupt is acknowledged