GE DS200TCEAG2B Emergency Overspeed Board

Part Number DS200TCEAG2B Manufacturer General Electric Country of Manufacture As Per GE Manufacturing Policy Series Mark V Function Module Availability In StockDS200TCEAG2B is an Emergency Overspeed Board manufactured and designed by General Electric. It is a part of the Mark V LM Series used in gas turbine control systems. The high-speed protection circuitry is implemented by the Emergency Overspeed Board (TCEA), which is often referred to as the Protective Processor and is housed in the Protective Core P1. FUNCTIONAL DESCRIPTION The three TCEA boards that make up the P1 core are known as the X, Y, and Z processors. These boards each provide signals for flame detection, automatic synchronization, high and low shaft speed, and more. Through the JX1 connector on the TCEA board in position one, (X), the signals are scaled and conditioned before being written over the IONET to the STCA board in the "R1" core. The JX1 and JX2 connections through X are used by the TCEA boards in positions three (Y) and five (Z) to transport information. The R1 core's I/O Engine takes information from the three TCEA boards to perform a median selection on the three values before sending the results to the Control Engine through the COREBUS.

Each TCEA board delivers a trip signal to a separate relay, and the TCEA boards communicate emergency trip signals to the Turbine Trip Board (TCTG). Relay driver level voting is performed by the three relays on the TCTG board, and the outcome determines whether the TCTG board trips the device. Each TCEA board includes a dedicated power supply and diagnostics for that power source. TCEA CONFIGURATION HARDWARE Hardware jumpers J1 and J31 on the TCEA board are utilized for factory testing. For IONET termination resistors, use J2 and J3. Each TCEA board's IONET address is set using the hardware jumpers J4, J5, and J6. J12 through J21 for the high-pressure shaft and J8 through J11 and J22 through 27 for the low-pressure shaft are used to confirm the Overspeed trip frequency settings. The I/O configuration software is used to perform the actual configuration. Hardware jumpers J28 and J29 make "Z" always vote for a trip on an emergency Overspeed. The stall timer is enabled by J30. SOFTWARE The hardware jumper settings for trip frequency are calculated using the IO Configuration Editor, which is also used to establish the base speed and Overspeed values for the high and low-pressure shafts. The IO Configuration Editor is used to specify the permitted values for auto-synchronization and the pulse rate data from the Ultra Violet (UV) flame detectors, as explained below.

TCEA TURBINE OVERSPEED CIRCUIT The hardware jumpers validate the Overspeed settings, and the I/O configuration constants control the emergency Overspeed trip level settings. The PTBA terminal board in the "P1" core for the emergency Overspeed circuit receives the shaft speed magnetic pick-ups. In order to use the signals in the Control Sequence Program for primary Overspeed, the PTBA board parallels the signals to the "R1" core. The TCEA board uses I/O configuration constants to determine shaft speed. To identify an Overspeed trip condition, the TCEA board checks the computed shaft speeds with the I/O configuration constants trip values. If a trip condition is found, the circuit will trip the unit by de-energizing the Emergency Trip Relays (ETRs) on the Turbine Trip Board (TCTG). Hardware jumpers J28 and J29 are set up to always request an Overspeed emergency trip.

J28 and J29 work with the embedded software and the IONET address jumpers J4, J5, and J6. The TCEA board will always vote in favor of an emergency Overspeed trip if it receives a message from IONET indicating that it is aboard. As a result, the system has a dual redundant system for Overspeed emergency trip scenarios. The unit will trip in response to a request for an emergency Overspeed trip from either X or Y. J28 and J29 need to be set to the same value for X and Y.