GE DS200STCAG1A ARCNET LAN Driver Board

Part Number ds200stcag1a Manufacturer General Electric Country of Manufacture As Per GE Manufacturing Policy Series Mark VI/VIe Function Module Availability In StockDS200STCAG1A is a Turbine Communication Board developed by GE. It serves as the I/O cores' IONET master. There is an STCA board for every I/O core. The bus connections J1 and J3 are used to read signals from the various connectors, condition them, and then write them to the I/O Engine on the UCPB daughterboard. The JEE connector is used to write the signals to the COREBUS connections on the QTBA or CTBA boards. DS200STCAG1A Connectors Power is distributed to each I/O core via 2PL from the TCPS board. The 3PL data bus connects the STCA and TCQA boards in the cores and, the STCA, TCQA, and TCQE boards in the core, and the STCA, TCCA and TCCB boards in the core. Conditioned signals are sent across the 3PL connector to the COREBUS. To the TCQC boards in cores, and to the CTBA board in, there is an 8PL -I/O connector. The serial I/O signals, the ac and DC power monitoring signals (TCPD), the COM1 RS232 output signals, and an additional pulse rate magnetic pick up signal are examples of possible signals. I/O connector for the TCQC board: 19PL. Megawatt, generator, bus, and magnetic pick-up pulse rate signals from the high pressure shafts are only a few examples of the I/O signals. Signals from the power bus and neutral bus can also be transferred by this connector (TCPS).

Not every core will necessarily use the 19PL connection. On this connector, additional signals could be transmitted. The ARCNET signals from the UCPB daughterboard are interfaced in the IO cores by ARCNET. Signals utilized for the terminal interface on COM1 are RS232. FAN - Power supply for the fan that circulates air around the UCPB board's 486DX CPU. UCPB daughterboard connected through J1 bus. UCPB daughterboard connection via J3 bus. For the COREBUS, JEE-Communicates between the STCA board and the QTBA or CTBA terminal boards. Parallel 2PL connections using 2PLX. (Not typically used.) Configuration Hardware The factory test points are enabled by hardware jumper JP2. The voltage required for the flash EPROM is chosen by hardware jumper JP4. For details on the hardware jumper settings for this board, consult Appendix A and the operator interface's hardware jumper panel. Software. The I/O Configuration Editor on the operator interface is used to enter the I/O configuration constants for the pulse rate inputs, compressor stall detector, and synchronization settings. Pulse Rate Input Circuit The pulse rate inputs obtained from the TCQC board are scaled and conditioned by the STCA board. These signals come from magnetic pick-up devices, and the QTBA, TBQB, and/or PTBA terminal boards write their signals to the TCQC board. The high pressure shaft pulse rate inputs are read by the core.

Each core's pulse rate inputs are separate and serve various functions. Synch Check Circuit The 19PL connector is used to read the generator and bus voltage inputs from the TCQC board. These signals are sent from the core's PTBA terminal board to the core's TCTG board via the JN connection. The signals are then sent from the TCTG board to the TCQA board in the core through the JDR/S/T connectors to the JD connector.