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Home ⊙ NEWS ⊙ TEWS TQMC700 Reconfigurable FPGA with AD/DA & Digital I/O
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TEWS TQMC700 Reconfigurable FPGA with AD/DA & Digital I/O

From:TEWS | author:Mr.Chen | Time :2025-08-20 | 5 view: | Share:

Application Information

The TQMC700 is a VITA93.0 compatible single-width

QMC offering a user programmable AMD Artix 7 7A50T

FPGA.

The TQMC700 provides 16 ESD-protected 5V-tolerant

TTL lines. All I/O lines are individually programmable as

input or output. TTL I/O lines can be set to high, low, or

tristate. Each TTL I/O line has a pull-resistor to a common

programmable pull-up voltage that can be set to +3.3 V,

+5 V and GND.

The 18 bit ADC offers 8 input channels, each of them has

a sampling rate of up to 1 Msps. Each channel can be

operated in bipolar single-ended, unipolar single-ended

and bipolar differential mode. In the single-ended modes it

offers software selectable input voltage ranges of 0-5 V, 0

10 V, 0-12.5 V, ±2.5 V, ±5 V, ±6.25 V, ±10 V and ±12.5V.

In differential mode the input voltages are selectable

between ±5 V, ±10 V, ±12.5 V and ±20 V. There is a

flexible digital filter offering a oversampling ratio up to 256.

The DAC offers 4 channels of 16 bit analog outputs with

software selectable output voltage ranges of 0-5 V, 0-10

V, 0-10.8 V, ±5 V, ±10 V or ±10.8 V. The output voltage

range can be individually set per channel. The conversion

time is typ. 10 μs and the DAC outputs are capable to

drive a load of 2 kΩ, with a capacitance up to 4000 pF.

Each TQMC700 is factory calibrated. The calibration

information is stored in an on-board serial EEPROM

unique to each TQMC700 module.

The User FPGA is configured by a SPI flash. An in-circuit

debugging option is available via the QMC’s JTAG

interface for read back and real-time debugging of the

FPGA design (using the Vivado ILA).

User applications for the TQMC700 with 7A50T FPGA can

be developed using the design software Vivado Design

Suite HL WebPACK Edition.

TEWS offers a well-documented basic FPGA Example

Application design. It includes a constraints file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TQMC700. It implements PCIe to register mapping and

basic I/O. It comes as a Xilinx Vivado Design Suite project

with source code and as a ready-to-download bit stream.

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