GE VMIVME-1182 64-Channel Isolated Digital Input Board with Multifunctional Intelligent Controller

Features

The VMIVME-1182 is a 64-channel optically isolated digital input board that can detect Changes of State (COS) on any of the 64 inputs. This COS data can be used in Sequence-of-Events (SOE) acquisition. The board provides pulse accumulation data, time tag data, and programmable debounce for each input. A variety of interrupt options are available. Figure 1 on page 14 is a block diagram of the VMIVME-1182.

The VMIVME-1182 features are outlined below.

• 64 optically isolated inputs

• Multiple-functions available per channel:– SOE reporting– Pulse accumulation reporting– Time tag reporting– Programmable debounce times

• Available in 5 to 250VDC or 4 to 240VAC options

• Available in contact sensing or voltage sensing options

• 1500VDC or 1100VRMS channel-to-channel and channel-to-VME isolation (1minute)

• Pulse accumulation for up to 65.535 pulses per channel

• SOE monitoring on a channel-by-channel basis

• Debounce time software controlled on a channel-by-channel basis

• COS monitoring software controlled on a channel-by-channel basis

• A24/A16 addressing capability

• Supervisory bus access, nonprivileged bus access, or both

• Release-On-Acknowledge (ROAK) interrupts on all VME levels

Functional Description

The VMIVME-1182 provides COS detection on all of its 64 inputs. Each input may be software controlled to detect rising edges, falling edges, or both rising and falling edges, or it may be software controlled to ignore all changes for a given channel. In addition to COS detection, a variety of reporting and interrupt capabilities are available.

Each COS event may be stored in an SOE buffer where it is time tagged with a relative timer value of up to 65.535ms. The timer may be reset from the VME when desired.

Each COS event is counted in Pulse Accumulation Count registers, which record the number of events per channel.

VME interrupts may be issued on any level (software selectable), and a single byte vector is placed on the bus during the acknowledge cycle. The interrupt is cleared during the acknowledge (ROAK). Addressing is jumper selected and supports both A24 and A16 address space.

Address modifiers are jumper-selected and are decoded to support nonprivileged, supervisory, or both nonprivileged and supervisory access. A self-test is run automatically after a system reset, setting the Self-Test Complete bit in the Control

and Status Register (CSR) to one when completed. The board is initialized with the following default conditions:

• Fail LED is ON

• All interrupts are disabled

• All flags are cleared

• Test mode is enabled

• Interrupt Vector Register (IVR) is cleared

• COS registers are cleared

• Pulse Accumulation Interrupt (PAI) registers are cleared

• Input Debounce/Select Registers (DSRs) are cleared

• Input Pulse Accumulation Count (PAC) registers are cleared

• Time tag clock is set to zero (0) and stopped

• SOE maximum count is cleared

• SOE count is cleared

• SOE buffers contain test data, if self-test fails. If self-test passes, then the SOE buffers are cleared.

• Self-Test Complete bit is set in the CSR