NI PC-LPM-16/PnP Theory of Operation Multifunction I/O Board for the PC

Functional Overview

The following are the major components making up the

PC-LPM-16PnP:

• PC I/O channel interface circuitry

• Analog input and data acquisition circuitry

• Digital I/O circuitry

• Timing I/O circuitry

You can execute data acquisition functions by using the analog input

circuitry and some of the timing I/O circuitry. The internal data and

control buses interconnect the components. The theory of operation for

each of these components is explained in the remainder of this chapter.

The block diagram in Figure 3-1 shows a functional overview of the

PC-LPM-16PnP.

PC I/O Channel Interface Circuitry

The PC I/O channel interface circuitry consists of an address bus, a data

bus, interrupt lines, and several control and support signals. The

components making up the PC-LPM-16PnP PC I/O channel interface

circuitry are shown in Figure 3-2.

The circuitry consists of Plug and Play address decoders, data buffers,

I/O channel interface timing control circuitry, and interrupt control

circuitry. The circuitry monitors address lines SA4 through SA15 to

generate the board enable signal, and uses lines SA0 through SA3 plus

timing signals to generate the onboard register select signals and

read/write signals. The data buffers control the direction of data transfer

on the bidirectional data lines based on whether the transfer is a read or

write operation.

The interrupt control circuitry routes any enabled interrupts to the

selected interrupt request line. The PC-LPM-16PnP has six interrupt

request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9.

The PC-LPM-16PnP generates interrupts in three different situations:

• When an A/D conversion generates data that can be read from FIFO

• When an active low-level signal is detected on the EXTINT* line

• When a rising-edge signal is detected on counter 2 output

The PC-LPM-16PnP individually enables and clears each one of these

interrupts. For more detailed information on generating interrupts

externally, see the EXTINTEN bit of the Command Register 1

description in Appendix D, Register-Level Programming.

Analog Input and Data Acquisition Circuitry

The PC-LPM-16PnP has 16 channels of analog input with 12-bit

A/D conversion. Using the timing circuitry, the PC-LPM-16PnP can

also automatically time multiple A/D conversions. Figure 3-3 shows a

block diagram of the analog input and data acquisition circuitry.

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, a jumperselectable

gain stage, and a 12-bit sampling ADC. The 12-bit output is

sign-extended to 16 bits before it is stored in a 256-word deep FIFO memory.

The input multiplexer stage is made up of a CMOS analog input

multiplexer and has 16 analog input channels (channels 0 through 15).

With the input multiplexer stage, input overvoltage protection of

±45 V is available powered on, or ±35 V powered off.

The PC-LPM-16PnP uses a successive-approximation analog-to-digital

converter (ADC). Software-selectable gains of 0.5, 1, and 2 for the

input signal combined with the ADC’s fixed input range of

±5 V yield four useful analog input signal ranges, 0 to 10 V,

±5 V, 0 to 5 V, and ±2.5 V.

When an A/D conversion is complete, the ADC clocks the result into

the A/D FIFO. The A/D FIFO is 16 bits wide and 256 words deep. This

FIFO serves as a buffer to the ADC and has two benefits. First, any time

an A/D conversion is complete, the A/D FIFO saves the value for later

reading, and the ADC can start a new conversion. Secondly, the A/D

FIFO can collect up to 256 A/D conversion values before losing any

information, thus giving the software some extra time (256 times the

sample interval) to catch up with the hardware. If the A/D FIFO stores

more than 256 values without the A/D FIFO being read, an error

condition called A/D FIFO Overflow occurs and A/D conversion

information is lost.

The A/D FIFO generates a signal that indicates when it contains

conversion data. You can read the signal state from the PC-LPM-16PnP

Status Register 1.

The output from the ADC is in two’s complement format. In unipolar

input mode (0 to 10 V or 0 to 5 V input range configuration), the data

from the ADC is interpreted as a 12-bit positive number ranging from 0

to 4,095. In bipolar input mode (±5 or± 2.5 V input range configuration), 

the data from the ADC is interpreted as a two’s

complement number ranging from -2,048 to +2047. The ADC’s output

is always sign-extended to 16 bits by board circuitry so that data values

read from the FIFO are 16 bits wide.

The ADC on the PC-LPM-16PnP includes calibration circuitry that

makes it possible to minimize zero, full-scale, and linearity errors. The

ADC goes through a self-calibration cycle under software control. To

properly use this ADC auto-calibration feature, you need an accurate

input stage that does not introduce significant offset and gain errors.

The analog input stage on the PC-LPM-16PnP maintains the required

accuracy without trimpot adjustments.