GE PCI-5565PIORC Ultrafast Fiber Optic Reflective Memory with Interrupts

OVERVIEW

The PMC-5565PIORC* is the PMC-based product in GE Intelligent Platforms' Reflective Memory Real-Time Fiber Optic Network product family.

Two or more PMC-5565PIORCs, as well as other products in this family, can be integrated into a network using standard fiber optic cables.

Each board in the network is referred to as a "node".

Reflective memory allows computers, workstations, PLCs and other embedded controllers with different architectures and different operating systems to share data in real time.

The 5565 Series Reflective Memory (referred to as RFM-5565 in this manual) is fast, flexible, and easy to operate.

Data is transferred via write memory (SDRAM) that appears to exist globally on all boards on the network.

The on-board circuitry automatically performs data transfers to all other nodes with little or no host processor involvement.

Features

Features include

- High-speed, easy-to-use fiber optic network (serial 2.12 GBaud)

- 33 MHz 64-bit/32-bit compliant PCI bus, 3.3 V or 5.0 V logic levels

- 66 MHz 64-bit/32-bit compliant PCI bus, 3.3 V logic level

- Host processor does not participate in network operation

- Optional redundant operation modes

- Up to 256 nodes

- Up to 256 nodes up to 300 m to multimode fiber, up to 10 km to singlemode fiber

- Dynamic packet sizes from 4 to 64 bytes of data per packet

- Fiber-optic network transfer rates of 43 MByte/s to 170 MByte/s

- 128/256 MB bytes of SDRAM reflective memory, with optional parity checking

- Independent direct memory access (DMA) channels

- Four general-purpose network interrupts; each interrupt has 32 bits of data

- Configurable endian translation for multiple CPU architectures on the same network

- Selectable PCI PIO window sizes from 2 MB bytes to 64 MB bytes to full installed memory size

- Supported Operating Systems Supports Windows® 2000. Windows XP, Linux®, and VxWorks® operating systems.

- RoHS compliant

Comparison of PMC-5565PIORC and VMIPMC-5565

The PMC-5565PIORC combines the components of the classic VMIPMC-5565 into a single FPGA (Field Programmable Gate Array).

These components include PLX Technologies' PCI interface device, three separate small FPGAs, a transmit FIFO and a receive FIFO.

The PMC-5565PIORC adds greater design flexibility than the legacy VMIPMC-5565 and improves performance in at least three ways.

1. the PMC-5565PIORC has improved DMA burst and PIO single read access rates over the legacy VMIPMC-5565. 2. the PMC-5565PIORC has improved DMA burst and PIO single read access rates over the legacy VMIPMC-5565.

2. The PMC-5565PIORC's onboard SDRAM memory access bandwidth has been doubled, improving overall throughput. doubled, increasing overall throughput.

3. The PMC-5565PIORC can be field upgraded as new features are added.

The legacy VMIPMC-5565 contains a set of control registers in the PLX device and a separate set of RFM-specific control registers in the FPGA.

Since these two sets of registers are physically located in different devices, they are accessed through different memory areas.

On the other hand, the PMC-5565PIORC contains two sets of registers in the same FPGA. These two sets of registers could have been combined.

However, in order to maintain software continuity and backward compatibility, the two sets of registers are stored separately as in the classic VMIPMC-5565.

In addition, the individual bit functions within the registers (where applicable) remain compatible.

The PMC-5565PIORC does not include a second DMA engine.

As shown below, the PMC-5565PIORC has an optical transceiver and three LEDs on the front panel.

The port labeled "RX" is the receiver and the port labeled "TX" is the transmitter.The PMC-5565PIORC uses an "LC" type fiber optic cable.

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